1. Field of the Invention
The present invention relates to a design of a dual gate LDMOSFET device which reduces ON state resistance and avoids degradation of breakdown voltage and has application to a power integrated circuit.
2. Discussion of Related Art
A double polysilicon (double poly-si) process for fabricating CMOS integrated circuits is well known. For instance, a double poly-si process is described in U.S. Pat. No. 4,517,731, whose contents are incorporated herein by reference.
The conventional design of a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) requires making a tradeoff between the ON state resistance and the breakdown voltage. A modified design by Serag E.-D. Habib, U.K. patent 2,150,746A, Jul. 3, 1985, has made it possible to obtain both low ON state resistance and high breakdown voltage at the same time. This was achieved by using a semi-insulating poly-Si (SIPOS) layer over the oxide covering drift region. In the ON state, the potential distributed along the SIPOS can bias the drift region into an accumulation region, which greatly reduces the ON state resistance. The ON state resistance was shown to be able to decrease by a factor of 2-4. This accumulation region may be at a surface of the drift region.
In the OFF state, the SIPOS layer has no detrimental effect on the breakdown voltage. The drawback of this design is that the decrease of the ON state resistance is not maximized since the potential distribution along the SIPOS layer is set by the applied drain voltage and may not be changed easily.
It would, therefore, be desireable to provide a circuit which maximizes the decrease of the ON resistance and yet avoids degradation of breakdown voltage.